library ieee;
use ieee.std_logic_1164.all;

entity testbench_FA is
end testbench_FA;

architecture behavioral of testbench_FA is
component FA is
  port(
    A: in std_logic;
    B: in std_logic;
    Cin: in std_logic;
    S: out std_logic;
    Cout: out std_logic
  );
end component;

  signal A,B,Cin,S,Cout: std_logic:= '0';
  begin
    test_FA: FA port map( A, B, Cin, S, Cout);
    
    process is
      begin
        A <= '0';
        B <= '0';
        Cin <= '0';
        wait for 1 ns;
        if S/= '0' or Cout /= '0' then 
          ASSERT false
          REPORT " FA 000 error"
          SEVERITY failure;
        end if;

        A <= '0';
        B <= '1';
        Cin <= '0';
        wait for 1 ns;
        if S/= '1' or Cout /= '0' then 
          ASSERT false
          REPORT " FA 010 error"
          SEVERITY failure;
        end if;

        A <= '1';
        B <= '0';
        Cin <= '1';
        wait for 1 ns;
        if S/= '0' or Cout /= '1' then 
          ASSERT false
          REPORT " FA 101 error"
          SEVERITY failure;
        end if;    

    
        A <= '1';
        B <= '1';
        Cin <= '1';
        wait for 1 ns;
        if S/= '1' or Cout /= '1' then 
          ASSERT false
          REPORT " FA 111 error"
          SEVERITY failure;
        end if;
      end process;
    end architecture behavioral;        
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_RCA is
end entity testbench_RCA;

architecture behavioral of testbench_RCA is
	component RCA is
	port(
	  A   : in std_logic_vector(31 downto 0);
	  B   : in std_logic_vector(31 downto 0);
	  Cin : in std_logic;
	  Sum : out std_logic_vector(31 downto 0);
	  CO  : out std_logic;
	  V   : out std_logic
	);
	end component;
  signal A,B,S : std_logic_vector (31 downto 0);
  signal Cin,Cout,V: std_logic;
  begin
    rippleAdder: RCA port map (A,B,Cin,S,Cout,V);
      testSequence: process is
      begin
        A <= std_logic_vector(to_signed(15,32));
        B <= std_logic_vector(to_signed(15,32));
        Cin <= '0';
        wait for 1 ns;
        if to_integer(signed(S))/= 30 or Cout /= '0' or V/= '0' then 
          ASSERT false
          REPORT " RCA 15-15 error 1"
          SEVERITY failure;
        end if;    
        
        A <= std_logic_vector(to_signed(15,32));
        B <= std_logic_vector(to_signed(-15,32));
        Cin <= '0';
        wait for 1 ns;
        if to_integer(signed(S))/= 0 or Cout /= '1' or V/= '0' then 
          ASSERT false
          REPORT " RCA 15-15 error 0"
          SEVERITY failure;
        end if;    
        
      end process testSequence;
end architecture behavioral;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_sklansky is
end entity testbench_sklansky;

architecture behavioral of testbench_sklansky is
component sklansky is
   port(
	OpA	: in	std_logic_vector(31 downto 0);
	OpB	: in	std_logic_vector(31 downto 0);
	Cin	: in	std_logic;
	Result	: out	std_logic_vector(31 downto 0);
	Cout	: out	std_logic;
	V		: out	std_logic -- modification to include overflow logic
	);
end component;
  signal A,B,S : std_logic_vector (31 downto 0);
  signal Cin,Cout,V: std_logic;
  begin
    sklanskyAdder: sklansky port map (A,B,Cin,S,Cout,V);
      testSequence: process is
      begin
        A <= "11011010000011101101010011011100";
        B <= "00110100011101011111111010101000";
        Cin <= '0';
        wait for 1 ns;
        if S/= "00001110100001001101001110000100" then 
          ASSERT false
          REPORT " RCA 15-15 error 1"
          SEVERITY failure;
        end if;    
        
      end process testSequence;
end architecture behavioral;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_SLTU is
end entity testbench_SLTU;

architecture behavioral of testbench_SLTU is
	component SLTU is
	port(
	  CO  	 : in std_logic;
	  Cout   : out std_logic_vector(31 downto 0)	  
	);
	end component;
	component RCA is
	port(
	  A   : in std_logic_vector(31 downto 0);
	  B   : in std_logic_vector(31 downto 0);
	  Cin : in std_logic;
	  Sum : out std_logic_vector(31 downto 0);
	  CO  : out std_logic;
	  V   : out std_logic
	);
	end component;
	
  signal A,B,S,outs : std_logic_vector (31 downto 0);
  signal Cin,CO,V: std_logic;
  begin
    rippleAdder: RCA port map (A,B,Cin,S,CO,V);
	SetLTU: SLTU port map (CO,outs);
      testSequence: process is
      begin
        A <= "11001011100000010000110010111111";--2comp of "00110100011111101111001101000001";
        B <= "01101111011110010110010001000110";
        Cin <= '0';
        wait for 1 ns;
        if outs/= "00000000000000000000000000000001" then 
          ASSERT false
          REPORT " RCA 15-15 error 1"
          SEVERITY failure;
        end if;    
        
      end process testSequence;
end architecture behavioral;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_LogicUnit is
end entity testbench_LogicUnit;

architecture behavioral of testbench_LogicUnit is
	component bitwiseAND is
	port(
	  A   : in std_logic_vector(31 downto 0);
	  B   : in std_logic_vector(31 downto 0);
	  C   : out std_logic_vector(31 downto 0)
	);
	end component;
  signal A,B, ANDresult, ORresult, XORresult, NORresult: std_logic_vector(31 downto 0);
  begin
    logicAND: bitwiseAND port map(A,B,ANDresult);
      testSequence: process is
      begin
        A <= std_logic_vector(to_signed(0,32));
        B <= std_logic_vector(to_signed(1,32));
        wait for 1 ns;
        if to_integer(signed(ANDresult))/= 0 then 
          ASSERT false
          REPORT " AND 0-1 error"
          SEVERITY failure;
        end if;
      end process testSequence;
end architecture behavioral;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testShift is
end testShift;

architecture behavioral of testShift is
	component shiftLeft is
	port(
	  A   : in std_logic_vector(31 downto 0);
	  B   : in std_logic_vector(31 downto 0);
	  C   : out std_logic_vector(31 downto 0)
	);
	end component;
	component shiftRightLogical is
	port(
	  A   : in std_logic_vector(31 downto 0);
	  B   : in std_logic_vector(31 downto 0);
	  C   : out std_logic_vector(31 downto 0)
	);
	end component;
	component shiftRightArithmetic is
	port(
	  A   : in std_logic_vector(31 downto 0);
	  B   : in std_logic_vector(31 downto 0);
	  C   : out std_logic_vector(31 downto 0)
	);
	end component;
signal A,B,Csl,Csrl,Csra: std_logic_vector(31 downto 0);
	begin
		sl: shiftLeft port map(A,B,Csl);
		lsr: shiftRightLogical port map(A,B,Csrl);
		asr: shiftRightArithmetic port map(A,B,Csra);
		testSequence: process is
		begin
        A <= "10000100010011011110001101001011";
        B <= "01101110001010101010101110010001";
        wait for 1 ns;
        if Csra /= "00000000000001000111001101111000" then 
          ASSERT false
          REPORT " sll 1-1 error"
          SEVERITY failure;
        end if;
      end process testSequence;
end architecture behavioral;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.custom_types.all;

entity testBench_Mux16x1 is
end testBench_Mux16x1;

architecture behavioral of testBench_Mux16x1 is
	component Mux16x1 is
	port(
	  
	  Ins 	 	 : in bus16x32;
	  Op		 : in std_logic_vector(3 downto 0);
	  Outs  	 : out std_logic_vector(31 downto 0)
	);
	end component;
	signal Ins : bus16x32;
	signal Outs : std_logic_vector(31 downto 0);
	signal Op: std_logic_vector (3 downto 0);
  begin
	muxer: Mux16x1 port map(Ins,Op,Outs);
    testSequence: process is
      begin
        Op <= "0000";
		Ins(0) <= "11111111111111111111111111111111";
        wait for 1 ns;
        if Outs/= "11111111111111111111111111111111" then 
          ASSERT false
          REPORT " Mux 0000 error"
          SEVERITY failure;
        end if;      
		
		Op <= "0100";
		Ins(4) <= "11111111111111111111111111111111";
        wait for 1 ns;
        if Outs/= "11111111111111111111111111111111" then 
          ASSERT false
          REPORT " Mux 0100 error"
          SEVERITY failure;
        end if;      		
        end process testSequence;
end architecture behavioral;
---------------------------------------------------------------------------------